3rd Generation TCP Endpoint Achieves 76-nanosecond Latency

Algo-Logic's 3rd Generation TCP Endpoint IP-Core enables FPGA-implemented logic to directly communicate over 10 Gigabit Ethernet networks with remote hardware or software devices and includes a robust hardware application programming interface that supports multiple real-world accelerated finance use cases.

The mature, reliable, and network-tested TCP endpoint delivers ultra-low-latency of 76-nanoseconds with the highest possible TCP bandwidth at full duplex rates of 20 Gbps scalable to 40/100 Gbps. Circuits have been implemented on both Altera and Xilinx FPGA devices and are compatible for deployment with all widely deployed FPGA platforms including Terasic DE5Net, Solarflare AOE and NetFPGA 10G. Plans are underway to also certify the IP-Core on additional end-customer platforms, including the Bittware S5PH-Q and Nallatech P385 platforms.

The key TCP Endpoint features include:

  • 8,16, 32 TCP Sessions per instance with user-defined MAC, Port, and IP Addresses.
  • Small LogicFootprint: 6.7% ALMs for 32 TCP sessions in Stratix V A7 for each TOE.
  • High Throughput: Can send and receive small and large payloads including jumbo frames.
  • Full 10GE Line Rate (20 Gbps Duplex) in an architecture that scales to support 40GE and 100GE.
  • Low latency proxy model that allows true parallel processing of client and exchange traffic communicating with a single application session in FPGA logic.
  • OS independent GUI or UDP network API for control and configuration.

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