Full Order Book on Single FPGA

The Full Order Book performs all book building processing and reporting as logic inside a single FPGA. The Low Latency Order- Book is designed using the on-chip memory for customer book sizes with many thousands of open orders, a dozen symbols, and reporting of ten L-2 levels. For use-cases where millions of open orders, thousands of symbols, and unlimited levels need to be tracked, the Scalable Order Book is still implemented with a single FPGA but stores data in off-chip DDR3 memory.

The Full Order Book building process includes (i) maintaining L-3 order-level book, (ii) updating L-2 book with a default of 10 price levels, (iii) reporting the Top-of-book with the best bid/ask information, and (iv) displaying of the last trade. Tracking deep L-3 book with ultra-high performance is achieved using Algo-Logic’s proprietary, 150 Million Searches Per Second (MSPS), algorithmic EMSE-2 IP-Core. The depth of the constructed L-2 book is user-configurable via the application programmable interface. Unlike multi-FPGA or CPU-based competitor architectures; Algo-Logic’s single-FPGA platform architecture achieves deterministic, ultra-low-latency without jitter regardless of the number of tracked symbols at data rates of up to 10 Gbps.

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