Highlights

Positions

• CEO of Algo-Logic Systems
• Professor at Stanford University and Washington University
• Chief Scientist and Co-founder of Global Velocity
• Senior Network Engineer at National Center for Computing Applications
• Consultant at SAIC, IBM, and AT&T Bell Laboratories
• Developer of Founder of Gradebot.com and Developer of Web-Basket and on-grading tools

Research Experience

• Managed NetFPGA program as Consulting Associate Professor at Stanford University
• Led Reconfigurable Network Group as Associate Professor at Washington University
• Published 15 journal and 91 peer-reviewed papers
• Presented 14 workshops and 28 invited talks
• Authored 7 patents and 3 book chapters
• Served as chair or reviewer for 24 major conferences and journals
• Principal Investigator (PI) or co-PI on $10M+ in grants and university gifts

Teaching Experience

• Taught 11 tutorials and workshops for Stanford University
• Developed 3 graduate courses and taught 2 seminar courses at Washington University
• Ranked as excellent by students of undergraduate classes at the University of Illinois
• Advisor or co-advisor for 22 graduate students at Washington University and UIUC

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Research Contributions

• Designed the FPX: a port extender using Field Programmable Gate Array hardware
• Developed open-source NetFPGA hardware and training materials
• Enhanced security of the Internet with reconfigurable hardware

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Academic and Industry Positions

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Research Grants and Gifts

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Patents

1. Methods and systems for content detection in a reconfigurable hardware, Bharath Madhusudan and John W. Lockwood
   Filed: August 2005
   USPTO: 20060053295
2. Method and Apparatus for Detecting Predefined Signatures In Packet Payload Using Bloom Filters, Sarang Dharmapurikar, Praveen Krishnamurthy, Todd Sproull, John W. Lockwood
   Filed: August 2003
   USPTO: 2005/0086520
3. TCP-splitter: reliable packet monitoring methods and apparatus for high speed networks, David Schuehler, John W. Lockwood
   Filed: August 2002
   USPTO: 2003/0177253
4. Reliable Packet Monitoring Methods and Apparatus for High-Speed Networks, David Schuehler, John W. Lockwood
   Filed: August 2003
   USPTO: 2004/0049596
5. Methods, Systems, and Devices using Reprogrammable Hardware for High-Speed Processing of Streaming Data to Find a Redefinable Pattern and Respond Thereto, John W. Lockwood, Ronald Loui, James Moscola, Michael Pachos
   Filed: May 2002
   Awarded: August 15, 2006
   US Patent: 7,093,023
6. System and Method for Controlling Transmission of Data Packets Over an Information Network, Matthew P. Kulig, Timmy L. Brooks, John W. Lockwood, David K. Reddick
   Filed: October 2001
   USPTO: 2003/0110229
7. Scalable broad band input-queued ATM switch including weight driven cell scheduler, H. Duan, John W. Lockwood, and S. M. Kang
   Filed: October 22, 1996
   Awarded: July 13, 1999
   US Patent: 5,923,656

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Publications

Journal Papers in Peer-Reviewed, Full-Length, Refereed Publications

1. Implementing Ultra Low Latency Data Center Services with Programmable Logic by John Lockwood, Madhu Monga; IEEE Micro, July/August 2016, pp. 18-26.
2. NetFPGA: An Open Platform for Teaching How to Build Gigabit-rate Network Switches and Routers by Glen Gibb, John W. Lockwood, Jad Naous, Paul Hartke, and Nick McKeown; IEEE Transactions of Education, August 2008, Volume 51, Issue 3, pp. 364-369.
3. Reconfigurable Content-based Router Using Hardware-Accelerated Language Parser by James Moscola, Young H. Cho, and John W. Lockwood; Transactions on Design Automation of Electronic Systems (TODAES), Volume 13, Number 2, April 2008.
4. Fast and Scalable Pattern Matching for Network Intrusion Detection Systems by Sarang Dharmapurikar and John W. Lockwood, IEEE Journal on Selected Areas in Communications, (JSAC) Oct. 2006, Volume: 24, Issue: 10, pp. 1781-1792.
5. Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures by Shobana Padmanabhan, Phillip Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger Chamberlain, Ron K. Cytron, Jason Fritts, and John W. Lockwood; International Journal of Parallel Programming, Volume 33, Number 2-3, June 2005, pp. 115-136.
6. A Hardware-Accelerated System for Real-Time Worm Detection, by Bharath Madhusudan and John W. Lockwood, IEEE Micro, January 2005, Vol. 25, No. 1, pp. 60-69.
7. Deep Packet Inspection using Parallel Bloom Filters by Sarang Dharmapurikar, Praveen Krishnamurthy, Todd S. Sproull, John W. Lockwood; IEEE Micro, Vol. 24, No. 1, Jan 2004, pp. 52-61.
8. Architecture for a Hardware-Based, TCP/IP Content-Processing System by David V. Schuehler, James Moscola, John W. Lockwood; IEEE Micro, Vol. 24, No. 1, Jan 2004, pp. 62-69.
9. Automated Tools to Implement and Test Internet Systems in Reconfigurable Hardware by John W. Lockwood, Chris Neely, Chris Zuver, Dave Lim; SIGCOMM Computer Communications Review (CCR), Vol. 33, No. 3, July 2003, pp.103-110.
10. Scalable IP Lookup for Internet Routers by David E. Taylor, Jonathan S. Turner, John W. Lockwood, Todd S. Sproull, David B. Parlour, IEEE Journal on Selected Areas in Communications (JSAC), Vol. 21, No. 4, May 2003, pp. 522-534.
11. TCP Splitter: A TCP/IP Flow Monitor in Reconfigurable Hardware, David V. Schuehler, John W. Lockwood; IEEE Micro, Vol. 23, No. 1, Jan. 2003, pp. 54-59.
12. Protocol Wrappers for Layered Network Packet Processing in Reconfigurable Hardware by Florian Braun, John Lockwood, and Marcel Waldvogel; IEEE Micro, Volume 22, Number 3, Feb. 2002, pp. 66-74.
13. Dynamic Hardware Plugins (DHP): Exploiting Reconfigurable Hardware for High-Performance Programmable Routers by David E. Taylor, Jonathan S. Turner, John W. Lockwood, Edson L. Horta; Computer Networks, February 2002, Volume 38, Issue 3, pp. 295-310, Elsevier Science.
14. Scalable Optoelectronic ATM Networks: The iPOINT Fully Functional Testbed by John W. Lockwood, Haoran Duan, James J. Morikuni, Sung Mo Kang, S. Akkineni, Roy H. Campbell; IEEE Journal of Lightwave Technology, June 1995, pp. 1093-1103.
15. Matrix Unit Cell Scheduler (MUCS) for Input-Buffered ATM Swithesby Haoran Duan, John W. Lockwood, Sung Mo Kang; IEEE Communications Letters. Volume 2, Number 1, January 1998, pp. 20-23.
16. Scalable IP Lookup for Internet Routers by David E. Taylor, Jonathan S. Turner, John W. Lockwood, Todd S. Sproull, David B. Parlour, IEEE Journal on Selected Areas in Communications (JSAC), Vol. 21, No. 4, May 2003, pp. 522-534.

Full-Length Papers in Peer-Reviewed, Refereed Proceedings

1. Implementing Ultra Low Latency Data Center Services with Programmable Logic by John Lockwood, Madhu Monga; IEEE 23rd Annual Symposium on High Performance Interconnects (HotI 2015), August 27, 2015, Santa Clara, CA.
2. A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT) by John Lockwood, A. Gupte, N. Mehta, M. Blott, T. English and K. Vissers; IEEE 20th Annual Symposium on High Performance Interconnects (HotI 2012), August 21, 2012, Santa Clara, CA.
3. Encouraging Reusable Network Hardware Design by G. Adam Covington, Glen Gibb, Jad Naous, John Lockwood, Nick McKeown; IEEE International Conference on Microelectronics System Education (MSE'09), June 2009.
4. Supercharging PlanetLab - High Performance, Multi-Application, Overlay Network Platform by Jon Turner, Patrick Crowley, John Dehart, Amy Freestone, Brandon Heller, Fred Kuhms, Sailesh Kumar, John Lockwood, Jing Lu, Mike Wilson, Charles Wiseman, Dave Zar; SIGCOMM 2007, August 27-31, Kyoto, Japan.
5. Adaptive Thermoregulation for Applications on Reconfigurable Devices by Phillip H. Jones, James Moscola, Young H. Cho, John W. Lockwood; Proceedings of International Conference on Field-Programmable Logic and Applications (FPL), Amsterdam, Netherlands, August 27-29, 2007.
6. Prototyping Fast, Simple, Secure Switches for Ethane, Jianying Luo, Justin Pettit, Martin Casado, Nick McKeown, John Lockwood; IEEE Symposium on High Performance Interconnects (Hot Interconnects-15), Stanford, CA, August 22-24, 2007.
7. Empirical Performance Assessment Using Soft-Core Processors on Reconfigurable Hardware by Richard Hough, Praveen Krishnamurthy, Roger D. Chamberlain, Ron K. Cytron, John Lockwood, and Jason Fritts, in ACM FCRC: Workshop on Experimental Computer Science, San Diego, CA; June 13-14, 2007.
8. Sensitivity Analysis of Gigabit Concept Mining System by Andrew Levine, Ron Loui, John W. Lockwood, Young H. Cho; IEEE Aerospace Conference; Big Sky, MT; March 3-10, 2007; Paper 10.0801.
9. Hardware-Accelerated Parser for Extraction of Metadata in Semantic Network Content by James Moscola, Young H. Cho, John W. Lockwood; IEEE Aerospace Conference; Big Sky, MT, March 3-10, 2007, Paper 10.0702.
10. Streaming Hierarchical Clustering for Concept Mining by Moshe Looks, Andrew Levine, G. Adam Covington, Ronald P. Loui, John W. Lockwood, Young H. Cho; IEEE Aerospace Conference; Big Sky, MT, March 3-10, 2007; Paper 10.0701.
11. Management and Service Discovery in Satellite and Avionic Networks by Todd Sproull, John W. Lockwood, John Meier; IEEE Aerospace Conference; Big Sky, MT; March 3-10, 2007; Paper 10.1501.
12. Dynamic Optimization of Workload for FPGA Application using Thermal Measurements, by Phillip H. Jones, Young H. Cho, and John W. Lockwood, 20th IEEE/ACM International Conference on VLSI Design, Bangalore, India, January 6-10, 2007.
13. An Adaptive Frequency Control Method Using Thermal Feedback for Reconfigurable Hardware Applications by Phillip Jones, Young Cho, John Lockwood, IEEE International Conference on Field Programmable Technology (FPT), Bangkok, Thailand, Dec 13-15, 2006.
14. Fast Packet Classification Using Bloom Filters by Sarang Dharmapurikar, Haoyu Song, Jonathan Turner, John Lockwood, ACM Symposim on Architectures for Networking and Communications Systems (ANCS), San Jose, CA, Dec 4-5, 2006.
15. A Thermal Management and Profiling Method for Reconfigurable Hardware Applications by Phillip H. Jones, John W. Lockwood, Young H. Cho; 16th Annual Conference on Field Programmable Logic and Applications (FPL); Madrid, Spain, August 28-30, 2006; pp. 103-109.
16. High Speed Document Clustering in Reconifigurable Hardware by G. Adam Covington, Charles L.G. Comstock, Andrew A. Levine, John W. Lockwood, Young H. Cho; 16th Annual Conference on Field Programmable Logic and Applications (FPL); Madrid, Spain, August 28-30, 2006; pp. 411-417.
17. A Reconfigurable Architecture for Multi-Gigabit Speed Content-Based Routing by James Moscola, Young H. Cho, and John W. Lockwood, IEEE Symposium on High Performance Interconnects (Hot Interconnects-14), Stanford, CA, August 23-24, 2006, pp. 61-66.
18. Rethinking Hardware Support for Network Analysis and Intrusion Prevention by Vern Paxson, Krste Asanovic, Sarang Dharmapurikar, John Lockwood, Ruoming Pang, Robin Sommer, Nick Weaver; USENIX First Workshop on Hot Topics in Security (HotSec), Vancouver, B.C., July 31, 2006.
19. Automatic Application-Specific Microarchitecture Reconfiguration by Shobana Padmanabhan, Ron K. Cytron, Roger D. Chamberlain and John W. Lockwood; 13th Reconfigurable Architectures Workshop (RAW), Apr 25-26, 2006.
20. Context-Free Grammar based Token Tagger in Reconfigurable Devices by Young H. Cho, James Moscola, John W. Lockwood; Proceedings of International Workshop on Data Engineering (ICDE/SeNS), Atlanta, GA, April 3-7, 2006.
21. Hardware Accelerated Algorithms for Semantic Processing of Document Streams by John W. Lockwood, Stephen G. Eick, Justin Mauger, John Byrnes, Ron Loui, Andrew Levine, Doyle J. Weishar, Alan Ratner, IEEE Aerospace Conference, Big Sky, MT, March 4-11, 2006, Paper 10.0802.
22. Cycle-Accurate Microarchitecture Performance Evaluation by Richard Hough, Phillip Jones, Scott Friedman, Roger Chamberlain, Jason Fritts, John Lockwood, and Ron Cytron, In Proceedings of Workshop on Introspective Architecture, Austin, TX, February 2006.
23. Multi-pattern Signature Matching for Hardware Network Intrusion Detection Systems by Haoyu Song and John W. Lockwood, IEEE Globecom 2005, St. Louis, MO, Nov. 28, 2005, pp. CN-02-3.
24. Optimizing Memory Bandwidth of a Multi-Channel Packet Buffer by Sarang Dharmapurikar, Sailesh Kumar, John W. Lockwood, and Patrick Crowley; IEEE Globecom 2005, St. Louis, MO, Nov. 28, 2005, pp. CG-3-8.
25. Shape Shifting Tries for Faster IP Route Lookup by Haouy Song, Jonathan Turner and John Lockwood. Proceedings of the IEEE International Conference on Network Protocols (ICNP), Boston, MA, Nov. 6, 2005, pp. 358-367.
26. Fast and Scalable Pattern Matching for Content Filtering by Sarang Dharmapurikar, John Lockwood Proceedings of Symposium on Architectures for Networking and Communications Systems (ANCS), Princeton, NJ, Oct 2005.
27. Fast Hash Table Lookup Using Extended Bloom Filter: An Aid to Network Processing by Haoyu Song, Sarang Dharmapurikar, Jonathan Turner, John Lockwood; ACM SIGCOMM; Philadelphia, PA; August 21-26, 2005.
28. HAIL: A Hardware-Accelerated Algorithm for Language Identification by Charles M. Kastner, G. Adam Covington, Andrew A. Levine, John W. Lockwood; 15th Annual Conference on Field Programmable Logic and Applications (FPL); Tampere, Finland; August 24-26, 2005.
29. SIFT: Snort Intrusion Filter for TCP by Michael Attig and John W. Lockwood; IEEE Symposium on High Performance Interconnects (Hot Interconnects-13); Stanford, CA; August 17-19, 2005.
30. A Framework For Rule Processing in Reconfigurable Network Systems by Michael E. Attig and John W. Lockwood, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM); Napa, CA; April 17-20, 2005. [Slides]
31. IPSec Implementation on Xilinx Virtex-II Pro FPGA and Its Application by Jing Lu and John Lockwood, Reconfigurable Architectures Workshop (RAW), Denver, Colorado, April 5, 2005.
32. Transformation Algorithms for Data Streams by John W. Lockwood, Stephen G. Eick, Doyle J. Weishar, Ron Loui, James Moscola, Chip Kastner, Andrew Levine, Mike Attig, IEEE Aerospace Conference, Big Sky, Montana, March 2005.
33. Efficient Packet Classification for Network Intrusion Detection using FPGA by Haoyu Song and John W. Lockwood, International Symposium on Field-Programmable Gate Arrays (FPGA'05), Monterey, California, Feb 20-22, 2005. [Slides]
34. Wide-area Hardware-accelerated Intrusion Prevention Systems (WHIPS) by Todd Sproull and John Lockwood, International Working Conference on Active Networking (IWAN), October 27-29, 2004, Lawrence, Kansas, USA.
35. A Modular System for FPGA-based TCP Flow Processing in High-Speed Networks by David Schuehler, John Lockwood; 14th International Conference on Field Programmable Logic and Applications (FPL), Springer LNCS 3203, Antwerp, Belgium, August 2004, pp. 301-310.
36. Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs by Edson Horta and John W. Lockwood; 14th International Conference on Field Programmable Logic and Applications (FPL), Springer LNCS 3203, Antwerp, Belgium, August 2004, pp. 975-979.
37. Design of a System for Real-Time Worm Detection by Bharath Madhusudan and John Lockwood; 12th Annual Proceedings of IEEE Hot Interconnects (HotI-12); Stanford, CA, August, 2004, pp. 77-83.
38. Application of Hardware Accelerated Extensible Network Nodes for Internet Worm and Virus Protection by John W. Lockwood, James Moscola, David Reddick, Matthew Kulig, and Tim Brooks, International Working Conference on Active Networks (IWAN), Kyoto, Japan, December 2003.
39. System-on-Chip Packet Processor for an Experimental Network Services Platform by David Taylor, Alex Chandra, Yuhua Chen, Sarang Dharmapurikar, John Lockwood, Wenjing Tang, Jonathan Turner; Proceedings of IEEE Globecom 2003, December 2003.
40. Internet Worm and Virus Protection in Dynamically Reconfigurable Hardware by John W. Lockwood, James Moscola, Matthew Kulig, David Reddick, Tim Brooks, Military and Aerospace Programmable Logic Device (MAPLD), Washington DC, 2003, Paper E10, Sep 9-11, 2003. [Photos]
41. An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall by John W. Lockwood, Christopher Neely, Christopher Zuver, James Moscola, Sarang Dharmapurikar, and David Lim; Field Programmable Logic and Applications (FPL), Lisbon, Portugal, pp. 859-868 (Paper 14B), Sep 1-3, 2003.
42. A TCP/IP Based Multi-Device Programming Circuit, by David V. Schuehler, Harvey Ku, John Lockwood; Field Programmable Logic and Applications (FPL), Lisbon, Portugal, Paper P2.B, Sep 1-3, 2003.
43. Deep Packet Inspection Using Parallel Bloom Filters by Sarang Dharmapurikar, Praveen Krishnamurthy, Todd Sproull, John W. Lockwood; Symposium on High Performance Interconnects (HotI), Stanford, CA, USA, pp. 44-51, Aug. 20-22, 2003.
44. Architecture for a Hardware Based, TCP/IP Content Scanning System by David V. Schuehler, James Moscola, and John W. Lockwood; Symposium on High Performance Interconnects (HotI), Stanford, CA, USA, pp. 89-94, Aug. 20-22, 2003.
45. Implementation of a Streaming Content Search-and-Replace Module for an Internet Firewall by James Moscola, Michael Pachos, John W. Lockwood, Ron P. Loui; Symposium on High Performance Interconnects (HotI), Stanford, CA, USA, pp. 122-129, Aug 20-22, 2003.
46. Implementation of a Content-Scanning Module for an Internet Firewall by James Moscola, John Lockwood, Ronald P. Loui, Michael Pachos; Field-Programmable Custom Computing Machines (FCCM), Napa, CA, April 9-11, 2003. [Presentation], [Demo Night Photos], [Audience Photos]
47. Power Consumption of Customized Numerical Representations for Audio Signal Processing by Roger Chamberlain, Yen Hsiang Chew, Vuruna DeAlwis, Eric Hemmeter, John Lockwood, Robert Morley, Ed Richter, Jason White, and Huakai Zhang; Sixth Annual Workshop on High Performance Embedded Computing (HPEC), Massachusetts Institute of Technology Lincoln Laboratory, September 24-26, 2002.
48. Using PARBIT to implement Partial Run-Time Reconfigurable Systems by Edson L. Horta, John W. Lockwood, and Sergio T. Kofuji, International Conference on Field Programmable Logic and Applications (FPL), Montpellier, France, September 2-4, 2002, Paper 5A.4.
49. TCP-Splitter: A TCP/IP Flow Monitor in Reconfigurable Hardware by David V. Schuehler, John Lockwood; Proceedings of Hot Interconnects 10 (HotI-10), Stanford, CA, August 21-23, 2002, pp. 127-131.
50. Implementing a dynamically reconfigurable ATM switch on the VIRTEX FPGA of the FPX platform by Edson L. Horta, John W. Lockwood, Sergio T. Kofuji; Proceedings of SPIE, Vol. 4867, No. 7, Boston, MA, July 30, 2002.
51. Scalable IP Lookup for Programmable Routers by David E. Taylor, John W. Lockwood, Todd S. Sproull, Jonathan S. Turner, David B. Parlour; IEEE Infocom 2002, New York NY, June 23-27, 2002.
52. Dynamic Hardware Plugins in an FPGA with Partial Run-time Reconfiguration by Edson L. Horta, John W. Lockwood, David E. Taylor, David Parlour; Design Automation Conference (DAC), New Orleans, LA, June 10-14, 2002, Paper 24.2.
    
53. Design of a High Performance Dynamically Extensible Router by Fred Kuhns, John DeHart, Anshul Kantawala, Ralph Keller, John Lockwood, Prashanth Pappu, Jyoti Parwatikar, Ed Spitznagel, David Richards, David Taylor, Jon Turner, Ken Wong; DARPA Active Networks Conference and Exposition (DANCE), May 29-31 2002, San Francisco, CA.
54. Control and Configuration Software for a Reconfigurable Networking Hardware Platform by Todd Sproull, John W. Lockwood, David E. Taylor; IEEE Symposium on Field-Programmable Custom Computing Machines, (FCCM), Napa, CA, April 24, 2002.
55. A Resource-based Approach to MAC Layer Independent Hierarchical Link-Sharing in Wireless Local Area Networks by Lars Wischhof and John Lockwood; European Wireless 2002 (EW2002), Feb. 2002, Florence, Italy.
56. Wireless call admission control using threshold access sharing by Jay R. Moorman and John W. Lockwood; IEEE Global Telecommunications Conference (GLOBECOM 2001), Vol. 6, San Antonio, TX, November 25-29, 2001, pp. 3698-3703.
57. Reconfigurable router modules using network protocol wrappers by Florian Braun, John Lockwood, Marcel Waldvogel; FPL 2001, Belfast, Northern Ireland, UK, August 28, 2001, pp. 254-263.
58. Layered Protocol Wrappers for Internet Packet Processing in Reconfigurable Hardware by Florian Braun, John Lockwood, Marcel Waldvogel; Proceedings of Hot Interconnects 9 (HotI-9), Stanford, CA, Aug 22-24, 2001, pp. 93-98.
59. Evolvable Internet Hardware Platforms by John W. Lockwood, NASA/DoD Workshop on Evolvable Hardware (EHW'01), Long Beach, CA, July 12-14, 2001, pp. 271-279.
60. Dynamic Hardware Plugins (DHP): Exploiting Reconfigurable Hardware for High-Performance in Programmable Routers by David E. Taylor, Jonathan S. Turner, John W. Lockwood; IEEE OPENARCH 2001: 4th IEEE Conference on Open Architectures and Network Programming, Anchorage, AK, April 2001.
61. Reprogrammable Network Packet Processing on the Field Programmable Port Extender (FPX) by John W. Lockwood, Naji Naufel, Jon S. Turner, and David E. Taylor; ACM International Symposium on Field Programmable Gate Arrays (FPGA 2001), Monterey, CA, February 2001, pp. 87-93.
62. An Open Platform for Development of Network Processing Modules in Reprogrammable Hardware by John W. Lockwood; IEC DesignCon 2001, Santa Clara, CA, Jan. 2001, Paper WB-19.
63. Compensation Modeling for QoS Support on a Wireless Networks by Stefan Bucheli, Jay Moorman, John Lockwood, and Steve Kang: IEEE Global Telecommunications Conference (GLOBECOM 2000), November, 2000, San Francisco, CA.
    
64. Real-Time Prioritized Call Admission Control in a Base Station Scheduler by Jay Moorman, John Lockwood, and Steve Kang. IEEE/ACM Wowmom, August, 2000. Boston, MA.
65. Experimentation and Analysis for Unified Packet-based Wireless Networks by Jay Moorman and John Lockwood, IEEE 3G Wireless, June, 2000. San Francisco, CA, pp. 239-245.
66. Field Programmable Port Extender (FPX) for Distributed Routing and Queuing, by John W. Lockwood, Jon S. Turner, David E. Taylor; ACM International Symposium on Field Programmable Gate Arrays (FPGA 2000), Monterey, CA, February 2000, pp. 137-144.
67. Implementation of the Multiclass Priority Fair Queuing (MPFQ) Algorithm for Extending Quality of Service in Existing Backbones to Wireless Endpoints by Jay Moorman and John Lockwood; IEEE Global Telecommunications Conference (GLOBECOM 1999), Rio De Janeiro, Brazil, December 1999, pp. 2752-2757.
    
68. Design of a Flexible Open Platform for High Performance Active Networks by Sumi Choi, John Dehart, Ralph Keller, John Lockwood, Jonathan Turner and Tilman Wolf; Allerton Conference, Champaign, IL, 1999.
69. Implementation of Campus-wide Wireless Network Services using ATM, Virtual LANs, and Wireless Basestations by John W. Lockwood; IEEE Wireless Communications and Networking Conference (WCNC). September 21-23, 1999, New Orleans, LA, Paper TA3.3.
70. Multiclass Priority Fair Queuing for Hybrid Wired/Wireless Quality of Service Support by Jay Moorman and John W. Lockwood; IEEE Mobicom/WoWMoM, August 20, 1999, Seattle, WA, pp. 43-50.
71. ABR Architecture and Simulation for an Input-Buffered and Per-VC Queued ATM Switch by Matthias Bossardt, Sueng-Yong park, John W. Lockwood, Sung-Mo Kang; IEEE Global Telecommunications Conference (GLOBECOM 1998), pp. 1817-1822, Sydney, Australia, Nov. 1998.
72. Providing Multicast Video on Demand using Native-mode Asynchronous Transfer Mode by John W. Lockwood, S. M. Kang, A. Hossain, J. Hiltenbrant, IEEE International Symposium on Circuits and Systems (ISCAS 1998), Monterey, CA, May, 1998.
73. A High-performance OC-12/OC-48 Queue Design Prototype for Input-buffered ATM Switches by Haoran Duan, John W. Lockwood, Sung Mo Kang, Jeff D. Will, IEEE Infocom '97, Kobe, Japan, April 7-11, 1997, pp. 20-28.
74. Development of the iPOINT Testbed for Optoelectronic Asynchronous Transfer Mode Networking by John W. Lockwood, S. M. Kang, S. G. Bishop, H. Duan, A. Hossain; International Conference on Information Infrastructure, April 25-28, 1996, Beijing, China, pp. 509-513.
75. An Efficient Input Queueing and Cell Scheduling Scheme for Scalable Ultra-Broadband Optoelectronic ATM Switching by Haoran Duan, John W. Lockwood, Sung Mo Kang; Emerging High Speed Local-area Networks and Wide-area Networks: Photonics East Conference, SPIE'95, Volume 2608, Philadelphia, Pennsylvania, October, 1995, pp. 107-108.
76. FPGA Prototype Queueing Module For High Performance ATM Switching by Haoran Duan, John W. Lockwood, Sung Mo Kang, Proceedings of the Seventh Annual IEEE International ASIC Conference, September, 1994, Rochester, New York, pp. 429-432.
77. The iPOINT Testbed for Optoelectronic ATM Networking, by John W. Lockwood, C. Cheong, Steve Ho, Ben Cox, Sung Mo Kang, Steve G. Bishop, Roy H. Campbell, Conference on Lasers and Electro-Optics (CLEO), May 1993, Baltimore, Maryland, pp. 370-371.

Short Papers Published in Peer-Reviewed, Refereed Conference Proceedings

1. Precise Latency Comparison Module for the NetFPGA, by Adwait Gupte and John W. Lockwood, 2nd North American NetFPGA Developer's Workshop, Stanford, CA, August 13, 2010.
2. AirFPGA: A software defined radio platform based on NetFPGA, by James Zeng, Adam Covington, and John Lockwood, 1st NetFPGA Developers Workshop, Stanford, CA, August, 2009.
3. A Packet Generator on the NetFPGA platform by G. Adam Covington, Glen Gibb, John Lockwood and Nick McKeown, IEEE Symposium on Field-Programmable Custom Computing Machines, April 5-7, 2009, Napa, CA.
4. NetFPGA - An Open Platform for Gigabit-rate Network Switching and Routing by John W. Lockwood, Nick McKeown, Greg Watson, Glen Gibb, Paul Hartke, Jad Naous, Ramanan Raghuraman, and Jianying Luo IEEE International Conference on Microelectronic Systems Education (MSE'07), June 3-4, 2007, San Diego, CA. [Presentation Slides]
5. Adaptive Control of FPGA Computation with Thermal Feedback by Phillip H. Jones, Young H. Cho, John W. Lockwood; The Syndicated, Q4, 2006.
6. Implementation of Network Application Layer Parser for Multiple TCP/IP Flows in Reconfigurable Devices by James Moscola, Young H. Cho, John W. Lockwood; 16th Annual Conference on Field Programmable Logic and Applications (FPL); Madrid, Spain, August 28-30, 2006; pp. 761-764.
7. Hierarchical Clustering using Reconfigurable Devices by Shobana Padmanabhan, Moshe Looks, Dan Legorreta, Young H. Cho, and John W. Lockwood; Proceedings of 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM); Napa, CA, USA, April 24-26, 2006; pp. 327-328.
8. Tools for In-Circuit Testing of On-Line Content Processing Hardware by Jeff Mitchell and John Lockwood; IEEE Computer Society International Conference on Microelectronic Systems Education (MSE'05), Anaheim, CA, June 2005.
9. Use of a Soft-Core Processor in a Hardware/Software Codesign Laboratoryby Roger Chamberlain, John Lockwood, Saurabh Gayen, Richard Hough, and Phillip Jones; IEEE Computer Society International Conference on Microelectronic Systems Education (MSE'05), Anaheim, CA, June 2005.
10. Microarchitecture Optimization for Embedded Systems by David Schuehler, Benjamin Brodie, Roger Chamberlain, Ron Cytron, Scott Friedman, Jason Fritts, Phillip Jones, Praveen Krisnamurthy, John Lockwood, Shobana Padmanabhan, Huakai Zhang, Eighth Annual Workshop on High Performance Embedded Computing (HPEC), Massachusetts Institute of Technology Lincoln Laboratory, September 28-30, 2004.
11. Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures by Shobana Padmanabhan, Phillip Jones, David V. Schuehler,
    Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger Chamberlain, Ron K. Cytron, Jason Fritts, and John W. Lockwood; Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES); Washington DC; Sept. 22, 2004.
12. Implementation Results of Bloom Filters for String Matching by Michael Attig, Sarang Dharmapurikar, and John Lockwood; In Proceedings of: IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, April 20-23, 2004. [Poster]
13. Secure Remote Control of Field-programmable Network Devices by Haoyu Song, Jing Lu, John Lockwood, James Moscola; In Proceedings of: IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, April 20-23, 2004. [Poster]
14. Internet Worm and Virus Protection for Very High-Speed Networks by John W. Lockwood, Seventh Annual Workshop on High Performance Embedded Computing (HPEC), Massachusetts Institute of Technology Lincoln Laboratory, September 23-25, 2003. [Presentation]
15. Internet-based Tool for System-on-Chip Integration by David Lim, Christopher E. Neely, Christopher K. Zuver, John W. Lockwood; IEEE Computer Society International Conference on Microelectronic Systems Education (MSE'03), Anaheim, CA, June 2003.
16. Internet-based Tool for System-On-Chip Project Testing and Grading by Christopher E. Neely, Christopher K. Zuver, John W. Lockwood; IEEE Computer Society International Conference on Microelectronic Systems Education (MSE'03), Anaheim, CA, June 2003.
17. Hot Interconnects 10 - Thinking Beyond the Internet, Guest editor introduction, IEEE Micro, Volume 23, Issue 1, Jan. 2003, pp. 8-9.
18. Platform and Methodology for Teaching Design of Hardware Modules in Internet Routers and Firewalls by John W. Lockwood; IEEE Computer Society International Conference on Microelectronic Systems Education (MSE'01), Las Vegas, NV, June 17-18, 2001, pp. 56-57.
    
19. Automated Team Project Management and Evaluation Through Interactive Web Modules by John W. Lockwood, IEEE Computer Society International Conference on Microelectronic Systems Education (MSE'99), Arlington, VA, July 19-21, 1999, pp. 26-27.
20. Distributed Learning via the World Wide Web Through Interactive Modules by John W. Lockwood; IEEE Computer Society International Conference on Microelectronic Systems Education (MSE'97), Arlington, VA, July 21-23, 1997, pp. 101-102.

Book Chapters

1. "Network Packet Filtering" by John W. Lockwood, Chapter 31 in Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation, Edited by Scott Hauck and Andre DeHon, ISBN-13: 9780123705228, Elsevier, 2007.
2. "Information Processing at Very High-Speed Data Ingestion Rates" by J. Brian Sharkey, Doyle Weishar, John W. Lockwood, Ron Loui, Richard Rohwer, John Byrnes, Krishna Pattipati, David Cousins, Michael Nicolletti, Stephen Eick; Chapter 4 in Emergent Information Technologies and Enabling Policies for Counter Terrorism, Edited by Robert Popp and John Yin, ISBN-13: 9780471776154, IEEE Press/Wiley, 2006, Pages 75-104.
   
3. "Logic Synthesis for Field Programmable Gate Array (FPGA) Technology" by John W. Lockwood, chapter in The VLSI Handbook, Edited by: W. K. Chen; ISBN-13: 9780849341991; New York: CRC Press LLC, 2006.

Workshops and Tutorials

1. Cloud Scale Key Value Store in FPGA, The Future of FPGA-Acceleration in Cloud and Datacenters, Workshop at IEEE Symposium on Field-Programmable Custom Computing Machines, May 6, 2020
2. NetFPGA Workshop in Brno presented as two-day tutorial at the International Conference on Field Programmable Logic and Applications (FPL) by John W. Lockwood, G. Adam Covington, Jan Korenek, Martin Zadnik, Jiri Novotny, Brno, Czech Republic, September 3-4, 2009.
3. Building Gigabit-rate Routers with the NetFPGA, a full-day tutorial in the NetFPGA World-wide tutorial series presented by John W. Lockwood, G. Adam Covington, Jan Korenek, Martin Zadnik, Jiri Novotny, Brno, Czech Republic, September 5, 2008. [Slides], [Photos]
4. Building Gigabit-rate Routers with the NetFPGA presented by John W. Lockwood, Glen Gibb, and Adam Covington; SIGCOMM Tutorial; Seattle, WA, August 17, 2008.
5. Stanford University-NetFPGA Summer Camp presented by John Lockwood, Glen Gibb, Adam Covington, Jad Naous, Sara Bolouki; Stanford, CA, August 4-8, 2008.
6. Hands-on with the NetFPGA to build a Gigabit-rate Routers at Indian Institute of Science (IISc) presented by John W. Lockwood, Jad Naous, and Kuruvilla Varghese; Bangalore, India, May 15-16, 2008.
7. Hands-on with the NetFPGA to build a Gigabit-rate Router at Beijing Jaiotong University presented by John W. Lockwood, Jianying Luo, Kevin Xie, Walkie Que, and Defeng Li; Beijing, China, Apr. 23, 2008.
8. NetFPGA: Hands-on with the NetFPGA to build a Gigabit-rate Router by John W. Lockwood, Gerald Adam Covington, Andrew Moore; presented at EuroSys 2008; Glasgow, Scotland; Mar. 31, 2008.
9. Hands-on with the NetFPGA to build a Gigabit-rate Router at NICTA presented by John W. Lockwood, Glen Gibb, Jad Naous; presented at the University of New South Wales (UNSW), Sydney, Australia, Feb. 6, 2008.
10. NetFPGA: Hands-on with the NetFPGA to build a Gigabit-rate Router by Nick McKeown, John W. Lockwood, Jad Naous, Glen Gibb, Adam Covington; presented at IEEE Hot Interconnects (HotI) - Symposium on High-Performance Interconnects; Stanford University, Stanford, CA; August 24, 2007.
11. NetFPGA: An Open-source Hardware Platform for Networking Research and Teaching by Nick McKeown, John W. Lockwood, Jad Naous, and Glen Gibb; presented at ACM SigMetrics 2007: International Conference on Measurement and Modeling of Computer Systems; San Diego, CA; June 12, 2007.
12. Liquid Architecture by Phillip Jones, Shobana Padmanabhan, Daniel Rymarz, John Maschmeyer, David V. Schuehler, John W. Lockwood, and Ron K. Cytron; International Parallel and Distributed Processing Symposium: Workshop on Next Generation Software (NSF-NGS); Santa Fe, NM, April 26, 2004, Paper: W10-NSFNGS-13.
13. June 2002 FPX Workshop by John W Lockwood, Todd Sproull, James Moscola, David Schuehler, Dave Lim, Sarang Dharmapurikar, Chris Neely, Gigabit Kits Workshop, Saint Louis, MO, June 19-20, 2002.
14. January 2002 FPX Workshop by John W Lockwood, David Taylor, James Moscola, Todd Sproull, Dave Lim, Gigabit Kits Workshop, Saint Louis, MO, January 3-4, 2002.
15. August 2001 FPX Workshop by John W Lockwood, Henry Fu, Todd Sproull, Sarang Dharmapurikar, Edson Horta, Dave Lim, Gigabit Kits Workshop, Saint Louis, MO, August 15-16, 2001.
16. January 2001 FPX Workshop by John W Lockwood, David E. Taylor, Todd Sproull, Sarang Dharmapurikar, Florian Braun, Gigabit Kits Workshop, Saint Louis, MO, January 11-12, 2001.

Technical Reports and Thesis

1. A Collision Detection Chip on Reconfigurable Hardware by Nuzhet Atay, John W. Lockwood, Burchan Bayazit; Washington University Dept. of Computer Science and Engineering; Technical Report WUCS-2005-033, 2005.
2. Design and Implementation of a String Matching System for Network Intrusion Detection using FPGA-based Bloom Filters by Sarang Dharmapurikar, Michael Attig, John W. Lockwood, Washington University Dept. of Computer Science and Engineering: Technical Report WUCS-2004-012, 2004.
3. Multiflow TCP, UDP, IP, and ATM Traffic Generation Module by Eliot I. Sinclair, John W. Lockwood, WUCSE-2003-24, April 24, 2003.
4. System-on-Chip Packet Processor for an Experimental Network Services Platform by David Taylor, Alex Chandra, Yuhua Chen, Sarang Dharmapurikar, John Lockwood, Wenjing Tang, Jonathan Turner, WUCSE-2003-22, April 22, 2003.
5. Usage of the Statistics Counter Plus Component in Networking Hardware Modules by Michael Attig, John Lockwood; Washington University, Department of Computer Science, Technical Report WUCS-02-25, August 2002.
6. Implementation of a Pipelined Control Cell Processor by Michael Attig and John Lockwood; Washington University, Department of Computer Science, Technical Report WUCS-02-24, August 2002.
7. Statistic Counter for Networking Hardware Modules by Michael Attig and John Lockwood; Washington University, Department of Computer Science, Technical Report WUCS-02-20, July 2002.
8. Field Programmable Port Extender (FPX) User Guide: Version 2.2 by John Lockwood; Washington University, Department of Computer Science, Technical Report WUCS-02-15, June 2002.
9. Packet Scheduling for Link-Sharing and Quality of Service Support in Wireless Local Area Networks by Lars Wischhof and John Lockwood; Washington University, Department of Computer Science, Technical Report WUCS-01-35, November 2001.
10. Scalable IP Lookup for Programmable Routers by David Taylor, John W. Lockwood, Todd Sproull, and David B. Parlour; Washington University, Department of Computer Science, Technical Report WUCS-01-33, October, 2001.
11. Synthesizable Design of a Multi-Module Memory Controller by Sarang Dharmapurikar and John Lockwood; Washington University, Department of Computer Science, Technical Report WUCS-01-26, October 2001.
12. Implementation of an Open Multi-Service Router by Fred Kuhns, John Dehart, Ralph Keller, John Lockwood, P. Pappu, J. Parwatikar, Ed Spitznagel, Dave Richards, Dave Taylor, Jon Turner, and Ken Wong; Washington University, Department of Computer Science, Technical Report WUCS-01-20, August 2001.
13. The FPX KCPSM Module: An Embedded, Reconfigurable Active Processing Module for the Field Programmable Port Extender (FPX) by Henry Fu and John W. Lockwood, Washington University, Department of Computer Science, Technical Report WUCS-01-14, July 2001.
14. PARBIT: A Tool to Transform Bitfiles to Implement Partial Reconfiguration of Field Programmable Gate Arrays (FPGAs) by Edson Horta and John W. Lockwood; Washington University, Department of Computer Science, Technical Report WUCS-01-13, July 2001.
15. Layered Protocol Wrappers for Internet Packet Processing in Reconfigurable Hardware by Florian Braun, John W. Lockwood, Marcel Waldvogel; Washington University, Department of Computer Science, Technical Report WUCS-01-10, July 2001.
16. OBIWAN - An Internet Protocol Router in Reconfigurable Hardware by Florian Braun, Marcel Waldvogel, and John Lockwood; Washington University, Department of Computer Science, Technical Report WUCS-01-11, July 2001.
17. "Hello World": A Simple application for the Field Programmable Port Extender (FPX) by John Lockwood and David Lim; Washington University, Department of Computer Science, Technical Report WUCS-00-12, July 2000.
    
18. Parallel FPGA Programming over Backplane Chassis by John Lockwood, Tom McLaughlin, Tom Chaney, Yuhua Chen, Fred Rosenberger, Alex Chandra, Jon Turner; Washington University, Technical Report WUCS-00-11, June 12, 2000.
    
19. Design and Implementation of a Multicast, Input-Buffered ATM Switch for the iPOINT Testbed by John W. Lockwood; PhD Dissertation, University of Illinois at Urbana-Champaign, Department of Electrical and Computer Engineering, 1995, UMI Number: 9625160.
20. The iPOINT Testbed for Optoelectronic ATM Networking by John Lockwood, University of Illinois at Urbana-Champaign, Department of Electrical and Computer Engineering, Technical Report: UILU-ENG-93-0401, May 1993.
    
21. SMAX: Simple Multicast ATM for XUNET by John Lockwood, AT&T Bell Labs Technical Report, A Scalable, Modular Framework to support ATM Applications, October 1994.
22. Proposed Mbone/XUNET Extensions by John Lockwood, AT&T Bell Labs Technical Report, October 1993.
    

Talks and Presentations

1. Algorithms in Logic for Ultra Low Latency Networking: Full Stack Applications in FPGAs. IEEE Hot Interconnects: Gold Sponsor Talk. August 19, 2021. Video
2. Half Billion IOPs in a 1U Redis Server with FPGA Acceleration, RedisConf 2020, May 12, 2020 (video)
3. From Glue Logic to the Basis of AI, Trading Systems. An Evolutionary Look at FPGA Software/Systems, The Next FPGA Platform, January 22, 2020, San Jose, CA
4. Algo-Logic's Real Time Energy Management System, SC19, November 25, 2019, Denver, CO
5. Scale-Out Machine Learning and Real-time Inference Accelerated by FPGA Key-Value Store, The Cube, SC17, November 9, 2017
6. Highlights from the 1st Asia NetFPGA Workshop, NEC, Tokyo, Japan, June 18, 2010.
7. Building Networks With Open, Reconfigurable Hardware, CFI 2010- 5th International Conference on Future Internet Technologies, Seoul, Korea, June 17, 2010.
8. Building Networks with Open, Reconfigurable Hardware, 1st Asia NetFPGA Developer's Workshop, Daejeon, Korea, June 14, 2010.
9. Experience with the NetFPGA Program, FPGA 2010 Pre-Conference Workshop on Open-Source for FPGA, Monterey, CA, February 21, 2010.
10. NetFPGA meets BWRC and Roach: Exploring ways to integrate Internet Routing with Software Defined Radio, UC Berkeley, BWRC, March 17, 2009.
11. Implementing Line-rate Services for Gigabit Networks with the the NetFPGA, distinguished lecture series invited talk by John W. Lockwood, UCSD: Department of Computer Science and Engineering, Feb. 9, 2009.
12. A quick introduction to Gigabit-speed programamble networking with the NetFPGA, invited talk by John W. Lockwood for University of Cambridge, Computer Laboratory, Cambridge, U.K, July 29, 2008.
13. The NetFPGA: An open platform for full-rate data processing on Gigabit-speed networks, invited talk by John W. Lockwood for Imperial College, Department of Computing, London, U.K., July 28, 2008.
14. The NetFPGA: An open platform for full-rate data processing on Gigabit-speed networks, invited talk by John W. Lockwood for Centre for Electronics Design and Technology, India Institute of Science (IISc), Bangalore, India, May 13, 2008.
15. The NetFPGA: An open platform for high-speed data processing and clean-slate network prototyping, invited talk by John W. Lockwood for Intel China Research Center, Beijing, China. Apr. 28, 2008.
16. Research and Teaching with the NetFPGA, invited talk by John W. Lockwood for: Professor Workshop for the Xilinx University Program, Guilin, China, Apr. 26, 2008.
17. A Quick Update on High Speed Networking Systems, invited talk by John W. Lockwodo for: Huawei, Beijing, China, Apr. 24, 2008.
18. NetFPGA: An open platform for high-speed data processing, invited talk by John W. Lockwood for: University of Glasgow, Glasgow, Scotland, Mar. 27, 2008.
19. NetFPGA: An open platform for high-speed data processing, invited talk by John W. Lockwood for: Agilent Laboratories South Queensferry, United Kingdom, Mar. 26, 2008.
20. >Prototyping Hardware-accelerated Routing on the NetFPGA, invited talk by John W. Lockwood for: Juniper Networks, Sunnyvale, CA, Mar. 21, 2008.
21. Rebuilding the Internet with Reconfigurable Hardware, invited talk by John W. Lockwood for: University of California, Merced, California, Mar. 14, 2008.
22. NetFPGA: An open platform for High-speed data processing & Network traffic filtering, invited talk and demonstration by John W. Lockwood and Gerald Adam Covington at Agilent Laboratories, Santa Clara, CA, Sep. 24 2008.
23. NetFPGA: An Open Platform for Building Extensible Networks with Reconfigurable Hardware, invited talk by John W. Lockwood for PRESTO, Princeton University, May 31, 2007.
24. Liquid Architecture - Results of Optimization of the LEON, invited talk by John W. Lockwood for RAMP January 2007 Workshop, University of California, Berkeley, January 12, 2007.
25. Development of Next-generation Networks with Reconfigurable Hardware, invited colloquia by John W. Lockwood for University of California, Riverside: Department of Computer Science and Engineering, April 3, 2006.
26. Measurement and Filtering of TCP/IP traffic flows at OC-48 Rates using Reconfigurable Hardware, invited talk by John W. Lockwood at CAIDA of the University of California, San Diego, January 28, 2005.
27. Insecure Networks, invited talk by John Lockwood for Society of Women Engineers (SWE), St. Louis, MO, November 9, 2004.
28. Fast Content Processing in Reconfigurable Hardware Hardware, invited talk by John Lockwood for Crossbeam Systems, Boston, MA, September 13, 2004.
    
29. Intelligent Networks, invited talk by John Lockwood and Jack Meier for: Technology Gateway: IT Meeting, St. Louis, MO, April 8, 2004.
30. Evaluation and Testing of Quality of Service in Realistic, High-Performance Networks, invited talk by John Lockwood, Boeing - Quality of Service Summit, St. Louis, MO, February 16, 2004.
31. Application of Hardware Accelerated Extensible Network Nodes for Internet Worm and Virus Protection, invited seminar talk by John Lockwood, Old Dominion University, Norfolk, VA, January 30, 2004.
32. Techniques to Achieve Multi-Gigabit/second Internet Worm and Virus Protection with Extensible Hardware, invited talk by John Lockwood, Extreme Networks, Santa Clara, CA, January 23, 2004.
33. Security for Internet Infrastructure, invited panel talk by John Lockwood, TechConnect'03, St. Louis, MO, Oct. 2003
34. System-On-Chip Internet Firewall, invited talk by John Lockwood, IEEE Computer Society International Conference on Microelectronic Systems Education (MSE'03), Anaheim, CA, June 2003.
35. Extensible Networking in Reconfigurable Hardware, invited Colloquium by John Lockwood, Georgia Tech, Center for Experimental Research in Computer Systems Colloquium: Atlanta, GA, February 20, 2003.
36. Extensible Networking Technology, invited talk by John Lockwood, Boeing, Advanced Networking Working Group Meeting, Saint Louis, MO, February 11, 2003.
37. Network Processing in Reconfigurable Hardware by John W. Lockwood, OpenSig 2002, Lexington KY, October 17-18, 2002.
38. Dynamically Reconfigurable Networking Hardware Platforms by John W. Lockwood, NSF/Darpa Workshop on New Visions for Large-Scale Networks (LSN'01), Vienna, VA, March 12-14, 2001, Paper 63-LOC.
39. Rapid prototype of hardware-based networking modules on the Field-programmable Port Extender (FPX) by John W. Lockwood, NSF-PI Workshop on Networking, University of California, Irvine, November 1-3, 2000.
    

Demonstrations

1. Algo-Logic's Real-time Energy Management System in FPGA Logic, SC19, November 20, 2019, Denver, CO
2. Algo-Logic's Ultra Low Latency Tick-to-Trade System with Advanced Turbo Spreader, FIA Expo, October 17, 2018, Chicago, IL
3. Algo-Logic Demonstrates Scale-Out Machine Learning and Real-Time Inference Accelerated by FPGA Key Value Store, SC17, November 13, 2017, Denver, CO
4. Algo-Logic's Low Latency Key-Value Store, SC16, November 15, 2016, Salt Lake City, UT
5. Live Tick-to-Trade Demonstration, Flagg HPC Conference, September 22, 2014, New York, NY
6. A Packet Generator on the NetFPGA platform by G. Adam Covington, Glen Gibb, John Lockwood and Nick McKeown, IEEE Symposium on Field-Programmable Custom Computing Machines - Demo Night, April 6, 2009, Napa, CA.
7. NetFPGA Demonstration at the International Conference on Field Programmable Logic and Applications (FPL), Heidelberg, Germany, September 8-10, 2008. [Photos]
8. Hands-on tutorial of the NetFPGA at ACM SigMetrics 2007: International Conference on Measurement and Modeling of Computer Systems, San Diego, CA, June 12, 2007. [Slides] [Photos]
9. Live demonstration of FPX hardware at the FCCM exhibition by John W. Lockwood, Mike Attig, Haoyu Song, and Jing Lu; Napa, CA; Apr 21, 2004. [Demo Photos] [Conference Photos]
10. Internet Worm and Virus Proteuction with Extensible Networks, live demonstrations during annual review day at the Center for Security Technologies, by John W. Lockwood, Dave Schuehler, Mike Attig, and James Moscola, St. Louis, MO, Jan 26, 2004.
11. Internet Worm and Virus Protection in Dynamically Reconfigurable Hardware by John W. Lockwood, James Moscola, Matthew Kulig, David Reddick, Tim Brooks, at the Reagan Center for the Military and Aerospace Programmable Logic Device (MAPLD) Expo, Washington DC, 2003, Sep 9-11, 2003. [Photos]
12. Content-Scanning Module for an Internet Firewall by James Moscola, John W. Lockwood, at FCCM Demo Night, Napa, CA, April 9, 2003. [Photos]
13. Control and Configuration Software for a Reconfigurable Networking Hardware Platform by Todd Sproull and John W. Lockwood, at FCCM Demo Night, Napa, CA, April 24, 2002. [Photos]
14. Dynamic Hardware Plugins (DHPs) in an FPGA with Partial Run-time Reconfiguration (RTR) by Edson L. Horta and John W. Lockwood, at the Tenth ACM International Symposium of Field-Programmable Gate Arrays (FPGA 2002), Monterey, CA, February 24-26, 2002.

In the Press

1. Algo-Logic Systems: Time is Money, Capital Markets CIO Outlook Magazine, February 2019
2. End-to-End Solution for Acquiring, Fusing, and Visualizing Real Time Data, SC18, November 15, 2018, Dallas, TX
3. Accelerated processing teaches autonomous cars to drive in minutes, The Cube: SiliconANGLE, December 4, 2017
4. Algo-Logic Launches Third Generation FPGA Accelerated CME Tick-to-Trade System, May 10, 2017
5. CAPI Enabled Order Book, IBM Edge Conference, May 11, 2015, Las Vegas, NV
6. Gateware Defined Networking Solutions for Enterprise Networks, CEO/CFO Interviews, September 8, 2014
7. Gateware Defined Networking (R) GDN Technology, Talk Business 360, American Airlines, October 2013
8. Success with Synplicity and the Reconfigurable Network Group, Identify Success Story, October, 2006.
   
9. Recognition Engines: New computer designs process networked "streams" of data for better spam and virus detection, Scientific American, January 2006.
10. 42nd Design Automation Conference Student Design Contest Winners Announced - Chip Design Magazine, June 8, 2005
11. Debugging of an Internet Packet Scheduler Using the Identify Software, by Christopher K. Zuver and John W. Lockwood, The Syndicated, Volume 4, Issue 4, 2004.
12. Blocking SPAM requires another can of worms, St. Louis Post-Dispatch, June 18, 2004.
13. Global Velocity Inc., Midwest Technology Journal, May 2004.
14. Global Velocity closes on $1.5 Million Round, Silicon Valley biz ink (PR Newswire), April 27, 2004.
15. Device guards Net against viruses, Technology Research News, December 17, 2003.
16. System halts computer viruses, worms, before end-user stage, Washington University Record, Nov. 5, 2003.
17. Extensible Network Security Device Built with the Amplify Solution by John W. Lockwood, The Syndicated, Volume 3, Issue 3, 2003.
18. CSE beats odds, receives three NSF 2003 Information Technology Research grants, in WU Engineering News, Fall 2003, p. 7.
19. Washington University in St. Louis ranks 9th for National Universities with Doctoral programs, according to US News and World Reports 2004 rankings.
20. Washington U. professor offers a Sobig answer, Saint Louis Post-Dispatch, Front page, Sunday business section, August 24, 2003.
21. One Hour Repair - Hardware adds features must faster, Washington University Record, Vol. 27, Number 7, October 11, 2002.
22. Hot Interconnect wrestles with wire-speed challenges, CommsDesign, August 23, 2002.
23. FPGA Platform Fuels Study of Reconfigurable Networks, EE Times, Issue 1228, July 22, 2002.

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Education

University of Illinois, Department of Electrical and Computer Engineering

• PhD: August 1993 - October 1995
  • Thesis: Design and Implementation of a Multicast, Input-Buffered ATM Switch for the iPOINT Testbed:
    Presents the design of a novel input-buffered switch and details of the implemention using all Field Programmable Gate Array (FPGA) logic.
  • GPA: 5.0/5.0
• MS: August 1991 - May 1993
  • Thesis: The iPOINT Testbed for Optoelectronic ATM Networking
    
  • GPA: 5.0/5.0
• BS: August 1987 - May 1991
  • GPA: 4.7/5.0 (Technical: 4.9/5.0)
  • Honors & Dean's list
• Classwork
  • Computer Networking
  • Computer Architecture
  • Parallel Systems and Algorithms
  • Circuits and VLSI Design
  • Optics & Semiconductors

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Technical Skills

• Reprogrammable Logic: Designed, synthesized, tested, and implemented Field Programmable Gate Array designs in Xilinx and Altera devices
• Hardware Synthesis: VHDL and Verilog Simulation and Synthesis with Synplicity, Synopsys, ViewLogic, and Mentor Graphics tools
• Data Networking: Configuration of Cisco routers (IOS), Ethernet switches, and ATM to implement campus LANs and WAN links
• Programming: C++, C, X86 Assembly, Perl, Pascal
• Web/CGI/Database
  • Founder, developer, owner, programmer & operator of Gradebot.com
    • Designed and Implemented WebBasket electronic commerce tool.
    • Designed and Implemented Distributed Learning tools for automated grading of online homeworks and management of class projects and grades
    • Manage conference submissions and review process
  • Developed components of NetDocs (an Interactive, web-based tools for Network Mangement) for the NCSA: Network Development Group:
• Operating Systems: Self-administrator for LINUX server and Windows desktop systems

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Professional Service, Honors, and Awards

• Professional Society Leadership
  • Program Co-Chair, 1st Asia NetFPGA Developers Workshop, Daejeon, Korea, June 14, 2010
  • Program Chair, NetFPGA Developers Workshop, Stanford, CA, August 12-14, 2009
  • General Chair, Hot Interconnects 16, Symposium on High Performance Interconnects (2008)
  • Steering Committee, HotI Symposium on High Performance Interconnects (2004-2009)
  • Steering Committee, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) (2008-2009)
  • General Co-Chair, Hot Interconnects 15, Symposium on High Performance Interconnects (2007)
  • Symposium Chair, Advances for Networks & Internet, IEEE GlobeCom, November 2005
  • General Chair, MSE'05: International Conference on Microelectronic Systems Education (2005)
  • Panel Co-Chair, Field-Programmable Gate Arrays Conference (2005): FPGA Startups: Diamonds or Dust
  • General Chair, Hot Interconnects 11 Symposium on High Performance Interconnects (2003)
  • Program Chair, MSE '03: International Conference on Microelectronic Systems Education (2003)
  • Guest Editor, IEEE Micro: (Jan 2002, Jan 2003)
  • Program Chair, Hot Interconnects 10 Symposium on High Performance Interconnects (2002)
  • Program Co-Chair, Hot Interconnects 9: Symposium on High Performance Interconnects (2001)
  • Proceedings/Web Chair, MSE '01: International Conference on Microelectronic Systems Education (2001)
• Professional Society Service
  • Technical Program Committee, IEEE Symposium on High Performance Interconnects (Hot Interconnects) (2002-2005, 2008-2012)
  • Program Committee, Ninth ACM Workshop on Hot Topics in Networks (HotNets-IX) (2010)
  • Program Committee, Field-Programmable Gate Arrays (FPGA) (2004-2012)
  • Program Committee, Symposium on Architectures for Networking and Communications Systems(ANCS) (2008, 2009, 2010)
  • Session Chair, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) (2008, 2009)
  • Program Committee, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) (2007, 2008, 2009)
  • Program Committee, ACM SIGCOMM (2008)
  • Program Committee, International Conference on Field Programmable Logic and Applications (FPL) (2005, 2006, 2007)
  • Session Chair, International Conference on Field Programmable Logic and Applications (FPL) (2006)
  • Session Chair, Hot Interconnects 14 Symposium on High Performance Interconnects (2006)
  • Technical Program Committee, Intl. Working Conference on Active Networks (IWAN) (2002, 2003, 2004, 2005)
  • Session Chair, Field-Programmable Gate Arrays (FPGA) (2004, 2008)
  • Judge, Design Automation Conference (DAC): SIGDA PhD Forum & Student Design Contest (2003, 2004, 2005, 2006, 2007)
• Reviewer of Papers
  • IEEE Transactions on Networking
    
  • IEEE Transactions on Computers
  • Journal of Systems and Software
  • IEEE Transactions on Mobile Computing (TMC)
  • IEEE Micro
  • IEEE Transactions on Education
  • Cluster Computing Journal
  • The Computer Journal
  • International Conference on Field Programmable Logic and Applications (FPL)
  • ACM Transactions on Embedded Systems (TECS)
  • Workshop on Network Processors - NP2
  • IEEE Journal on Selected Areas of Communication (JSAC)
  • IEEE Transactions on Very Large Scale Integration Systems (TVLSI)
  • Computer Networks Journal
  • ACM Sigmetrics
  • Globecom
• Professional Society Membership
  • Association for Computing Machinary (ACM)
    • SIGDA: Design Automation
    • SIGCOMM: Data Communication
  • Institute of Electrical and Electronics Engineers (IEEE)
    • IEEE Computer Society
    • IEEE Communications Society
  • International Game Developers Association (IGDA)
  • Tau Beta Pi: Engineering Honor Society
  • Eta Kappa Nu: Electrical Engineering Honor Society