Algo-Logic is partnered with Altera, Nallatech, ReFLEX CES, BittWare, IBM, Juniper Networks, Terasic, Solarflare, and Xilinx to provide ideal hardware solutions for designs that demand high capacity and bandwidth memory interfacing, ultra-low latency communication, and power efficiency. Algo-Logic implements solutions on their FPGA cards to perform lookups with the lowest latency (less than 1 microsecond), highest throughput, and least processing energy.

Available Algo-Logic Solutions (varies by card)

  • Intel Programmable Acceleration Card

  • This PCIe*-based FPGA accelerator card provides the performance and versatility of FPGA acceleration and is one of several platforms supported by the Acceleration Stack for Intel® Xeon® CPU with FPGAs.

  • Xilinx Virtex UltraScale+ FPGA VCU1525

  • This PCIe® development board is accessible in the cloud and on-premise with the frameworks, libraries, drivers and development tools to support easy application programming with HLS, OpenCL™, C, C++ and RTL through the Xilinx SDAccel™ Development Environment.

  • Trade Server

  • Algo-Logic can provide full turn-key solutions using these servers to achieve the lowest possible latency Tick-to-Trade solutions.

  • Terasic DE5-Net

  • Terasic's DE5-Net card that is empowered with the top-of-the-line Altera Stratix V GX and designed for the most demanding high-end applications.

  • Nallatech P385

  • Nallatech's accelerator P385 card that can be targeted to a wide number of applications.

  • BittWare S5-PCIe-HQ

  • BittWare's half-length PCIe x8 card based on the high-bandwidth, power-efficient Altera Stratix V GX or GS FPGA.

  • Solarflare AOE

  • Combines a full-featured 10GbE server adapter with a state-of-the-art FPGA that allows users to determine which portions of code benefit most from hardware processing vs. software.

  • IBM POWER8 CAPI Order Book

  • Performs all feed processing and book building in logic inside a single Stratix V FPGA on the Nallatech P385 card. The system enables software to directly receive order book snapshots in the coherent shared memory with the least possible latency.